Sequential Circuits

Problem in Master Slave

We have a problem in master-slave flip-flops. Consider a RS Master-Slave Flip-flop and following waveforms are the expected output of RS flip-flop

While when we actually give the above inputs to RS master-slave flip-flop, we get the following outputs

And we see that at the 4th and 5th edge we have the wrong transitions. 

Why so?

Before the 4th negative edge, there is small R pulse which resets the output of Master RS flip-flop and after resetting the output of master RS flip-flop R goes low. Now we have S=0 & R=0 and output of master stays low and hence when transition of CLK occurs from 1 to 0, we have S=0 & R=1 (instead of S=1 & R=0) at the slave FF and hence final output is reset. So we notice that a high pulse at R has affected output even when pulse occurred much before the negative edge.

Before the 5th negative edge, a short high pulse occurs at S input of master due to which output of master is set to 1 and after some time S resets and we have S=0 & R=0 and hence output of master stays high and when CLK goes from 1 to 0, we have inputs of slave as S=1 & R=0 (instead of S=0 & R=1) and hence final output is set to 1. We again notice a pulse which occurs much before the edge and still affects the final output.

So we find a situation when a master-slave flip-flop doesn’t work as edge-triggered FF.  Similar problem we’ll face in JK flip-flop as we have a no change condition in both FFs. But we can realize a edge-triggered FF with D Flip-flop without this problem as:

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