Sequential Circuits

Maximum Frequency of the clock signal

To achieve the maximum frequency of the clock signal we can assume to start SETUP time immediately after the CLK to Q delay is finished.

              This would mean that we can have the next positive edge (CLK to Q delay + SETUP time) after the previous positive edge. And with 50% duty cycle, falling edge would be right in the middle of positive edges. Hence we get the total minimum time period and maximum frequency of the clock signal as

Tmin = CLK to Q delay + SETUP time

Fmax= 1/ Tmin = 1/( TCLK-to-Q + TSETUP)

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