Q- Can we design a MOD-6 counter using the above method? Ans: We firstly draw the state diagram And now we draw the table to represent the desired output of the combinational circuit to reset FFs as: Q2 Q1 Q0 OUTPUT 0 0 0 1 0 0 1 1 0 1 0 1 0 1 […]

# Tag: questions

## USING K-MAPS to design counter

Q- Design MOD-3 ripple counter using (a) Observing outputs (b) K-maps to design the circuit. Ans: (a)We can design the MOD 3 counter using 2 FFs as 3 is less than 4 i.e. 22 and greater than 2. We can see directly that as we have to reset the counter only after 2 i.e. when output is […]

## Counter other than MOD-2n

Q-Can we design a ripple counter other than MOD-2n? Ans: Yes we can. For this we’ll first design the counter with value which is multiple of 2 but greater than the count required. Then we use a combinational circuit to reset the counter after the required value of count is achieved. Let’s take an example: Design […]

## Q: Serial Data Transfer

Q- Design a circuit to transfer data serially from one shift register to other. Ans: If we have a N-bit shift register then we need only N clock cycles to shift those N-bits to the other register. If we apply more or less than this many clock cycles then our operation of shifting would not […]

## Q4: Maximum Frequency

Q- Find the maximum clock frequency of the following circuit and specifications of the different flip-flop are as T1 (setup) = 5ns T1 (hold time) = 4ns T1 (CLK to Q) = 9ns, T2 (setup) = 4ns T2 (hold time) = 3ns T2 (CLK to Q) = 7ns T3 (setup) = 4ns T3 (hold time) […]

## Q3: Maximum Frequency

Q- Find the maximum clock frequency of the following circuit and specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and maximum delay of the combinational circuit is T (c-delay) = 13 ns and delay of buffer is T (buf) = 2ns. Ans: There is […]

## Q2: Maximum frequency

Q- Find the maximum clock frequency of the following circuit and specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and maximum delay of the combinational circuit is T (c-delay) = 13 ns Ans: As input to first flip-flop is directly available and […]

## Q1: Timing Diagram

Q- We are given a D FF which is used as a divide by 2 circuit and specifications of the flip-flop are as: T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and circuit is as: Find Maximum frequency. Ans: I’ll recommend drawing the 1st edge of clock and then to […]

## Q: D-Flip-flop using MUX

Q- Can we implement the D-Flip-flop using MUX? Ans: Yes, we can. As we can derive a D FF from D latch by following circuit: So we implement the above circuit to get D ff from MUX as: The following D FF is a falling edged or negative edged Flip-flop. And we can implement the rising edge […]

## QUESTIONS: Flip flops/Latch

Q-What is the difference between LATCH & FLIP-Flop? Ans: We can easily find the answer after going through the theory given: Latches are level sensitive while flip-flops are edge sensitive devices Hence latches faces problems like glitches in the output while no such problem occurs in flip-flops. As we can see from different circuits given […]