**Q- Find the maximum clock frequency of the following circuit and specifications of the different flip-flop are as T1 (setup) = 5ns T1 (hold time) = 4ns T1 (CLK to Q) = 9ns, T2 (setup) = 4ns T2 (hold time) = 3ns T2 (CLK to Q) = 7ns T3 (setup) = 4ns T3 (hold time) = 4ns T3 (CLK to Q) = 9ns and delay of combinational circuit1 is 13 ns & of combinational circuit2 is 16ns in the following circuit.**

**Ans:** Now we to take care of following conditions while calculating maximum frequency of the circuit:

- Inputs of FF1 come directly hence only setup time of FF1 should be satisfied
- Various delays would matter for Inputs of FF2 wrt to the previous edge of FF1
- Various delays would matter for Inputs of FF3 wrt to the previous edge of FF2

Let’s represent all delays with the different clock edges:

Hence we get to know that

If we calculate minimum clock period (Tmin) considering conditions to be fulfilled for edge of FF1 then

**Tmin= T1 (setup) = 5 ns**

Considering conditions to be fulfilled for edge of FF2 then

**Tmin= T1 (CLK to Q) + cdelay1 + setup2 = 9 + 13 + 4 = 26 ns**

Considering conditions to be fulfilled for edge of FF3 then

** Tmin= T2 (CLK to Q) + cdelay2 + setup3 = 7 + 4 +16 = 27 ns**

Now if we take clock period as 5 ns then we’ll not be able to satisfy the condition at clock edge of FF2 & FF3 (As clock is common for all)

If we take clock period as 26 ns, then we’ll be satisfying the condition at FF1 & FF2 but conditions of FF3 would not be satisfied & hence we cannot take this as clock period.

But if we take clock period as 27 ns then we satisfy the condition at every clock edge.

Hence minimum clock period to satisfy every condition is Tmin = 27 and **maximum clock frequency we get is 1/ 27 = 3.7 MHz**