Sequential Circuits

Q1: Timing Diagram

Q- We are given a D FF which is used as a divide by 2 circuit and specifications of the flip-flop are as:

T (setup) = 5ns  T (hold time) = 4ns          T (CLK to Q) = 9ns and circuit is as:

Find Maximum frequency.

Ans: I’ll recommend drawing the 1st edge of clock and then to mark the various delays which we require for proper input to reach the flip-flops before the 2nd edge of the clock as: We know that we have to obey following conditions of setup & propagation time:

To get the minimum delay (maximum frequency of the circuit) , we eliminate the time between end of propagation time and starting of setup time and we get the clock waveform as:

Hence we get to know that minimum time period as:

T = T (setup) + T (CLK to Q) = 5 + 9 = 14 ns = 14 * 10-9 s

And the maximum frequency we get is 1/ T = 1 / 14 = 10/ 14 = 71.4 MHz

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