The full adder has 3 inputs and 2 ouputs. The first 2 inputs are the 2 bits a & b to add while the 3rd input c is the carry from the previous significant bit while the outputs are the same: sum S and the carry C. The following table shows the result of different combinations of inputs:

a              b             c              S(sum) C(carry)

0              0              0              0             0

0              1              0              1              0

1              0             0             1             0

1              1             0              0             1

0              0             1              1             0

0              1              1              0              1

1              0             1              0              1

1              1              1             1             1

K-map for the output variable SUM is as follow:

This circuit is a level 3 circuit as we also need inverters at level 1, then we have 4 3-input AND gates at level 2 and 4-input OR gate at level 3. So we need 3 gate delays (3Δ) to get the output for Sum.

K-map for the variable carry is as follow:

When we implement this circuit we see that this is a level 2 circuit as we have AND gates at level 1 and 3-input OR gate at level 2 and hence we need 2 gate delays (2Δ) to get carry output.

Lets now put the equations in different form:

S = ab’c’ + a’b’c + a’bc’ + abc = Σ (1,2,4,7)

= b’ (ac’ + a’c) + b (a’c’ + ac) = b’ (ac’ + a’c) + b (ac’ + a’c)’

=b’ (a xor c) + b (a xor c)’                              {We know (ac’ + a’c)’ = a’c’ + ac and a’c + ac’ = a xor c}

= b’z + z’b= b xor z                                           {z= (a xor c)}

= b xor a xor c

S = a xor b xor c

and C = ab + ac + bc = ab(c + c’) + ac (b + b’) + bc (a + a’) = abc + abc’ + abc + ab’c + abc + a’bc                      = abc +a’bc+ab’c+abc’= Σ(3,5,6,7)

So we can draw the circuits using XOR, NOT, AND & OR gates 