It is a combinational circuit which selects one of the 2^{n} input lines and transmits the information from that line to the output line. The selection of the input line depends upon the ‘n’ input selection lines. It is also called **data selector **and is also referred to by only **MUX.**

Smallest MUX we have is 2 to 1 mux which has 2 input lines, 1 output line and 1 selection line. We also have 4 to 1, 8 to 1 mux and so on

**Q- Implement the 2 to 1 MUX**

Ans: Here we have 2 input, 1 selection pin and 1 output pin and truth table is

SEL(s) Y

0 D0

1 D1

So the equation for MUX can be written as

Y = s’D0 + sD1

which can be implemented using gates as follow:

For a 4 to 1 MUX we have total of 6 inputs (4 input lines and 2 selection lines). So we’ll have 64 combinations. The block representation and the truth table is as:

a b Output (Y)

0 0 D0

1 0 D1

0 1 D2

1 1 D3

So the equation for MUX can be written as

Y = a’b’D0 + a’bD1 + ab’D2 + abD3 which can be implemented