## Synchronous Counter

In synchronous counters we have the same clock signal to all the flip-flops. MOD-4 Synchronous counter: We discuss here a 2-bit synchronous counter. We have the circuit for this as:s We have the initial outputs as Q0=0 & Q1=0. Whenever the first negative clock edge comes O/P of 1st FF becomes 1 as we have J & […]

## Glitch

A glitch is an unwanted pulse which gets generated due to little difference in the delays of signals. Whenever signals with glitches are used as clock then glitches causes unwanted triggering of the flip-flop.  e.g. We can see in the wave-forms given above for MOD-14 counter that there is a glitch in the Q2 signal […]

## Q: Design custom ripple counter

Q- Design the ripple counter whose output sequence is represented by the following state diagram. Ans: As we can see that it is a down counter so we’ll be using Q bar of all flip-flops as clock to next flip-flops (negative edged FFs). We draw the table as  Q2         Q1          Q0                          OUTPUT 0              0              0                              0 […]

## Down Counter (Reverse counting)

Here we’ll be counting in reverse order i.e. count would start from 15 to 0 and again value goes from 0 to 15. We just make a change in the circuit as we give Q bar to the CLK of next flip-flop or we use positive edged flip-flops and give Q to CLK of next […]

## Q: Design custom ripple counter

Q- Design the ripple counter whose output sequence is represented by the following state diagram. Ans: As it is a 3-bit counter hence we firstly arrange 3 FFs and now we design the combinational circuit to reset the counter at appropriate point.  Q2         Q1          Q0                          OUTPUT 0              0              0                              0 0              0              1                              1 0              1              […]

## Q: MOD 6 Counter

Q- Can we design a MOD-6 counter using the above method? Ans:  We firstly draw the state diagram And now we draw the table to represent the desired output of the combinational circuit to reset FFs as: Q2          Q1          Q0                          OUTPUT 0              0              0                              1 0              0              1                              1 0              1              0                              1 0              1              […]

## USING K-MAPS to design counter

Q- Design MOD-3 ripple counter using (a) Observing outputs (b) K-maps to design the circuit. Ans: (a)We can design the MOD 3 counter using 2 FFs as 3 is less than 4 i.e. 22 and greater than 2. We can see directly that as we have to reset the counter only after 2 i.e. when output is […]

## Counter other than MOD-2n

Q-Can we design a ripple counter other than MOD-2n? Ans: Yes we can. For this we’ll first design the counter with value which is multiple of 2 but greater than the count required. Then we use a combinational circuit to reset the counter after the required value of count is achieved. Let’s take an example: Design […]

## Ripple counter

We can attach more flip-flops to make larger counter. We just use more flip-flops in cascade and give output of first to the clock of 2nd and output of 2nd to clock of 3rd and so on. This way every flip-flop would divide frequency of the clock by 2 and hence we can obtain a divide by larger […]

## Asynchronous Counters: MOD-2 counter

If we see that flip-flop is a mod-2 counter with starting count as 0. If we connect J & K to HIGH and supply clock to the flip-flop, we’ll see that flip-flop would count pulses 0, then 1 and as it is a MOD-2 counter so it’ll reset and again count from 0.  And the […]