Q- Find the maximum clock frequency of the following circuit and specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and delay of other components is T (buf) = 2ns,ï¿½ ï¿½ T (AND) = 4 ns, T (OR) = 4 ns,ï¿½ ï¿½ ï¿½ ï¿½ T (NOT) = 2 ns in the following circuit.
Ans: We first need to calculate the maximum delay of combinational circuit so that proper input reaches the inputs of 2nd FF.
Delay of one path in combinational circuit is T (OR) + T (NOT) = 4 + 2 = 6 ns
Delay of other path in combinational circuit is T (NOT) + T (NOT) = 4 ns
We take maximum of those hence 6 ns.
Hence Clock time period T =T CLK to Q + cdelay + Setup time â€“clock delay for 2nd FF = 9 + 6 + 5â€“2 = 18ns Maximum Clock frequency = F max = 1/18 = 5.55 MHz