Let’s first now derive the D flip-flop from RS flip-flop which we have already done: We first write the truth table for required D flip-flop as Now we write the excitation table of given FF SR flip-flop as Now we need to make a arrangement so that we manipulate input D to inputs R, S […]
Sequential Circuits
Excitation table of Flip flops
Excitation of a flip-flop is actually exact opposite of what a truth table is. The truth table for the flip-flop gives us the output for the given combination of inputs and present output while an excitation table gives the input condition for the given output change. E.g. As in truth table we say for T […]
Characteristics Equation of Flip flops
RS Flip flops: The truth table for RS Flip-flop is as follow: Now let’s draw the K-map and get the equation for output Q. As the Qp and Qp bar are compliment of each other so we’ll consider only one of those in K-MAP D FLIP-FLOP: Truth table is as: The equation we get is JK FLIP-FLOP: The truth […]
Q4: Maximum Frequency
Q- Find the maximum clock frequency of the following circuit and specifications of the different flip-flop are as T1 (setup) = 5ns T1 (hold time) = 4ns T1 (CLK to Q) = 9ns, T2 (setup) = 4ns T2 (hold time) = 3ns T2 (CLK to Q) = 7ns T3 (setup) = 4ns T3 (hold time) […]
Q3: Maximum Frequency
Q- Find the maximum clock frequency of the following circuit and specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and maximum delay of the combinational circuit is T (c-delay) = 13 ns and delay of buffer is T (buf) = 2ns. Ans: There is […]
Q2: Maximum frequency
Q- Find the maximum clock frequency of the following circuit and specifications of the flip-flop are as T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and maximum delay of the combinational circuit is T (c-delay) = 13 ns Ans: As input to first flip-flop is directly available and […]
Q1: Timing Diagram
Q- We are given a D FF which is used as a divide by 2 circuit and specifications of the flip-flop are as: T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and circuit is as: Find Maximum frequency. Ans: I’ll recommend drawing the 1st edge of clock and then to […]
Maximum Frequency of the clock signal
To achieve the maximum frequency of the clock signal we can assume to start SETUP time immediately after the CLK to Q delay is finished. This would mean that we can have the next positive edge (CLK to Q delay + SETUP time) after the previous positive edge. And with 50% duty cycle, falling edge […]
Timing parameters of a flip flop
There are basically 3 types of factors which affect the working of a flip flop: 1. Setup Time: This is defined as minimum amount of time required for which an input should be stable just before the clock transition occurs. Suppose we have a positive edged JK flip-flop and setup time is t= 1ns seconds. If […]
Q: D-Flip-flop using MUX
Q- Can we implement the D-Flip-flop using MUX? Ans: Yes, we can. As we can derive a D FF from D latch by following circuit: So we implement the above circuit to get D ff from MUX as: The following D FF is a falling edged or negative edged Flip-flop. And we can implement the rising edge […]