We have a problem in master-slave flip-flops. Consider a RS Master-Slave Flip-flop and following waveforms are the expected output of RS flip-flop While when we actually give the above inputs to RS master-slave flip-flop, we get the following outputs And we see that at the 4th and 5th edge we have the wrong transitions. Why so? Before […]
Sequential Circuits
Master slave Flip flop
We use 2 separate latches to construct a master-slave flip-flop. One latch acts as a Master and other acts as a Slave. Both are level triggered latches but one is latched on positive level and other on negative level. Diagram of the RS master-slave flip-flop is as: First latch acts as a master and 2nd latch acts as […]
Edge Sensitive Latch (i.e. FLIP-FLOP)
Latches which are activated by the edge of the clock are called Flip-flops. If it is a positive edged flip-flop then inputs are accepted only when a LOW to HIGH transition occurs in the clock and if it is a negative edged flip-flop then inputs are accepted only when there is a HIGH to LOW transition in the clock […]
QUESTIONS: Flip flops/Latch
Q-What is the difference between LATCH & FLIP-Flop? Ans: We can easily find the answer after going through the theory given: Latches are level sensitive while flip-flops are edge sensitive devices Hence latches faces problems like glitches in the output while no such problem occurs in flip-flops. As we can see from different circuits given […]
Parameters of clock pulses
Note that we need the width of PRESET pulse, CLEAR pulse etc to be greater than some minimum values for proper operation of every flip-flop. This width is measured between 50% transition points of rising and trailing edges of the given signal. Setup and Hold time are measured w.r.t the activating clock edge. The Setup time is the […]
Asynchronous Inputs
There are two special inputs which are used to clear and preset the value of the flip-flop asynchronously which are usually called CLEAR and PRESET respectively. These inputs are called asynchronous or direct inputs because these signal don’t wait for the clock to come but can affect the output independent of the clock. These inputs can be of two […]
Timing Problem in Latches
Well in sequential circuits, paths exit between latches through combinational circuits from one latch to other or from output of latch to input of same latch. When we give a feed back to input of same latch then we face a timing problem as shown: Suppose we have the following circuit: In this circuit when […]
T Latch
This latch is obtained from JK by connecting both the inputs. This is also known as Toggle latch as output is toggled if T=1. The truth table is: The circuit diagram of T latch is as follow:
JK Latch
This is very similar to RS latch but the ambiguous state has been eliminated and output is fed back to the AND gates. Also in this latch we get a complimented output when both the inputs are 1. Inputs are designated as J and K. The circuit diagram is as follow: Let’s now try to […]
D Latch
As we have already discussed that when ever we have both R & S equal to 1 we witness an ambiguous state. Hence to avoid this we have made an arrangement in which we’ll never have both R & S equal. We connect the two inputs with an inverter between them as shown below: This […]