Q- We are given a D FF which is used as a divide by 2 circuit and specifications of the flip-flop are as: T (setup) = 5ns T (hold time) = 4ns T (CLK to Q) = 9ns and circuit is as: Find Maximum frequency. Ans: I’ll recommend drawing the 1st edge of clock and then to […]
Digital Electronics
Maximum Frequency of the clock signal
To achieve the maximum frequency of the clock signal we can assume to start SETUP time immediately after the CLK to Q delay is finished. This would mean that we can have the next positive edge (CLK to Q delay + SETUP time) after the previous positive edge. And with 50% duty cycle, falling edge […]
Timing parameters of a flip flop
There are basically 3 types of factors which affect the working of a flip flop: 1. Setup Time: This is defined as minimum amount of time required for which an input should be stable just before the clock transition occurs. Suppose we have a positive edged JK flip-flop and setup time is t= 1ns seconds. If […]
Q: D-Flip-flop using MUX
Q- Can we implement the D-Flip-flop using MUX? Ans: Yes, we can. As we can derive a D FF from D latch by following circuit: So we implement the above circuit to get D ff from MUX as: The following D FF is a falling edged or negative edged Flip-flop. And we can implement the rising edge […]
Problem in Master Slave
We have a problem in master-slave flip-flops. Consider a RS Master-Slave Flip-flop and following waveforms are the expected output of RS flip-flop While when we actually give the above inputs to RS master-slave flip-flop, we get the following outputs And we see that at the 4th and 5th edge we have the wrong transitions. Why so? Before […]
Master slave Flip flop
We use 2 separate latches to construct a master-slave flip-flop. One latch acts as a Master and other acts as a Slave. Both are level triggered latches but one is latched on positive level and other on negative level. Diagram of the RS master-slave flip-flop is as: First latch acts as a master and 2nd latch acts as […]
Edge Sensitive Latch (i.e. FLIP-FLOP)
Latches which are activated by the edge of the clock are called Flip-flops. If it is a positive edged flip-flop then inputs are accepted only when a LOW to HIGH transition occurs in the clock and if it is a negative edged flip-flop then inputs are accepted only when there is a HIGH to LOW transition in the clock […]
QUESTIONS: Flip flops/Latch
Q-What is the difference between LATCH & FLIP-Flop? Ans: We can easily find the answer after going through the theory given: Latches are level sensitive while flip-flops are edge sensitive devices Hence latches faces problems like glitches in the output while no such problem occurs in flip-flops. As we can see from different circuits given […]
Parameters of clock pulses
Note that we need the width of PRESET pulse, CLEAR pulse etc to be greater than some minimum values for proper operation of every flip-flop. This width is measured between 50% transition points of rising and trailing edges of the given signal. Setup and Hold time are measured w.r.t the activating clock edge. The Setup time is the […]
Asynchronous Inputs
There are two special inputs which are used to clear and preset the value of the flip-flop asynchronously which are usually called CLEAR and PRESET respectively. These inputs are called asynchronous or direct inputs because these signal don’t wait for the clock to come but can affect the output independent of the clock. These inputs can be of two […]